SADRAM (Symbolically Addressable DRAM) introduces a revolutionary memory architecture that combines symbolic and traditional linear addressing, allowing DRAM to directly perform tasks like sorting, indexing, and symbolic data access. By integrating a logic layer with DRAM using Thru-Silicon Vias (TSVs), Sadram reduces CPU memory traffic, enhances energy efficiency, and improves system performance. Its sequencer-based design maintains sorted data, supports variable-length records, and enables complex operations, all while minimizing latency and power usage.
SADRAM (Symbolically Addressable DRAM) introduces a revolutionary memory architecture that combines symbolic and traditional linear addressing, allowing DRAM to directly perform tasks like sorting, indexing, and symbolic data access. By integrating a logic layer with DRAM using Thru-Silicon Vias (TSVs), Sadram reduces CPU memory traffic, enhances energy efficiency, and improves system performance. Its sequencer-based design maintains sorted data, supports variable-length records, and enables complex operations, all while minimizing latency and power usage.
This paper, SADRAM Arithmetic in C++, presents a C++ extension that introduces the 'sart' (sorted array) data type. This extension enables symbolic addressing and hardware-level sorting within DRAM, optimizing CPU memory traffic and energy consumption while improving database operations, sparse array handling, and numerical accuracy.
The paper, SADRAM: A New Memory Addressing Paradigm, explains how Sadram reduces CPU memory traffic by embedding symbolic addressing directly into DRAM. By integrating a logic layer with DRAM via Thru-Silicon Vias (TSVs), SADRAM enables sorting, indexing, and symbolic data access within memory, cutting latency, saving power, and improving system efficiency. This hybrid approach uses sequencer-based parallel processing to maintain sorted data structures and supports advanced applications such as database indexing, sparse arrays, and numerical accuracy control.
For a more in-depth understanding, you can access the full article through the ACM Digital Library link provided above or here below in the embedded pdf..
Sadram A new Memory Addressing Paradigm.pdf
SADRAM’s architecture integrates a logic layer directly with DRAM using Thru-Silicon Vias (TSVs)—vertical interconnects that enable high-speed, low-latency communication between processing and memory. This hybrid design reduces data movement between the CPU and DRAM, cutting power consumption by 70% and accelerating tasks like sorting and indexing by 2.5x compared to traditional systems. Inspired by Samsung’s Aquabolt architecture, Sadram’s TSVs minimize physical distance between components, enabling parallel row-wide computations within DRAM itself.
Key Innovations:
0x1A3F) with human-readable keys (e.g., "customer_id"), streamlining database operations and reducing CPU overhead.Sequencer-Cells